1. Field of the Invention
The present invention relates to an exposure pattern or mask suitable for use in an electron beam exposure process and to an inspection method and a manufacturing method for an exposure pattern or mask.
2. Description of Related Art
Miniaturization of recent semiconductor devices advances further and exceeds the limit of a resolution of an optical lithography system. In order to overcome this, fine patterning techniques have been developed which use a charged particle beam, such as an electron beam, and an ion beam to expose and draw a micro circuit pattern.
A conventional, direct drawing method utilizing electron beam exposure, however, requires a large amount of data when micro patterns are used for an LSI (large scale integrated) circuit having a high integration density. This results in a long drawing time and a low productivity (throughput).
In order to address this drawback, an electron beam aligner or an ion beam aligner has been proposed which irradiates an electron beam or an ion beam to a transfer mask to form a circuit pattern on a wafer with the beam passed through holes (pattern openings) of the transfer mask.
Exposure techniques of this type include, for example, an electron beam projection lithography using a high energy electron beam (refer to EPL: Electron-beam Proximity Lithography, H. C. Pfeiffer, Jpn. J. Appl. Phys. 34, 6658 (1995)), a low energy electron beam proximity projection lithography using a low energy electron beam (refer to LEEPL: Low Energy Electron-beam Proximity Projection Lithography, T. Utsumi, U. S. Pat. No. 5,831,272 (3, Nov. 1998)), an ion beam projection lithography using an ion beam (refer to IPL: Ion-beam Lithography, H. Loeschner et al., J. Vac. Sci. Technol. B19, 2520 (2001)), and other techniques.
An electron beam transmission mask (projection mask) used with these aligners, e.g., an LEEPL stencil mask, has a structure such as that shown in the plan view of FIG. 10A and the cross sectional view of FIG. 10B taken along line X-X′ shown in FIG. 10A. This stencil mask 67 has a membrane (thin film) having a thickness of 100 nm to 10 μm and formed with pattern openings 59. For example, the membrane (thin film) 51 of the stencil mask 67 having a thickness of 100 nm to 10 μm in thickness has a plurality of through holes (pattern openings) 59 having a width of 0.03 μm to 0.04 μm through which an electron beam is transmitted. In FIGS. 10A and 10B, only several pattern openings 59 are drawn for the purposes of drawing simplicity. The membrane 51 is supported by a silicon (Si) wafer (support substrate) 56. The Si wafer 56 is formed on an SiO2 film 55 formed around and outside the pattern openings 59 and having an opening 61 of 20 to 40 mm in diameter and has an opening 60 larger in size than the opening 61 of the SiO2 film 55.
As shown in FIG. 11, in an exposure process using the stencil mask 67, for example, the stencil mask 67 is disposed on a photoresist layer 57 formed on a wiring material layer 54 to be patterned, the wiring material layer being formed on an SiO2 film 55 on a semiconductor substrate 58. In this state, an electron beam 71 is emitted and passed through the pattern openings 59 of the membrane 51 of the stencil mask 67 to expose the photoresist layer 57 in a predetermined pattern. A photoresist pattern 57 left through development is used as a mask to dry etch the wiring material layer 54 and form a wiring pattern.
If the stencil mask 67 has, for example, a rectangular ring pattern opening 59 such as shown in FIG. 12A, a central area 51a serving as an electron beam absorber area falls out and cannot maintain the pattern opening. If the stencil mask has a leaf-shaped opening pattern (not shown), the shape of the opening pattern cannot be maintained stably, because this opening pattern is of a cantilever structure. These pattern openings are unable to be formed or difficult to be formed.
In order to form an object pattern opening 59 on a wafer, a so-called complementary division method has been introduced. Namely, the pattern opening 59 is geometrically divided into two masks 67A and 67B having divided opening patterns 59A and 59B, respectively, as shown in FIG. 12B, and are complementarily overlaid on the wafer, as shown in FIG. 12C.
FIGS. 13A to 14C illustrate a process of fabricating the stencil mask 67. As shown in FIG. 13A, on an Si wafer (support substrate) 56, an SiO2 film 55 and a membrane 51 made of Si or SiC are sequentially deposited to predetermined thicknesses.
As shown in FIG. 13B, a resist layer 63 having a predetermined pattern is formed on the Si wafer 56. A partial region of the Si wafer 56 is removed down to the surface of the SiO2 film 55 by dry etching to form an opening 60 and a support column 70 which partitions each mask quadrant.
As shown in FIG. 13C, after the resist pattern 63 is removed, by using the Si wafer 56 and support column 70 as a mask, a partial region of the SiO2 film 55 is removed down to the surface of the membrane 51 by dry etching to form an opening 61.
As shown in FIG. 14A in the up-side-down state of FIG. 13C, a resist layer 63 is formed on the membrane 51 and processed to have a predetermined pattern.
More specifically, openings 64 are formed through the membrane 51 to form a mask pattern portion 62 above the openings 60 and 61.
Next, as shown in FIG. 14B, by using the resist pattern 63 as a mask, the membrane 51 is dry etched to form through holes in the area corresponding to the mask pattern portion 62 to thereby form mask pattern openings 66.
Thereafter, as shown in FIG. 14C, the resist pattern 63 on the membrane 51 is removed so that a stencil mask 67 can be formed.
It is important to inspect whether the stencil mask has the pattern openings 66 just as designed.
In one example of a mask inspection apparatus and method, by utilizing an electron beam aligner without utilizing an additional inspection apparatus, it is possible to inspect whether there is any defect of a mask. {Refer to Patent Document 1: Japanese Unexamined Patent Publication No. 2001-153637 (p. 3, 28th line in right column to p. 5, 2nd line in right column, FIG. 2)}
In another example of a mask inspection apparatus and method, a mask pattern defect is inspected in the following manner. The mask pattern that is to be inspected is two-dimensionally scanned with an electron beam to obtain mask pattern transmission electric signals. From these electric signals, a mask pattern signal corresponding to the shape of the mask pattern is obtained. This mask pattern signal is compared with the CAD (Computer Aided Design) signal corresponding to a CAD figure to be used for mask pattern fabrication, and based upon this comparison result, the mask pattern defect is inspected. {Refer to Patent Document 2: Japanese Unexamined Patent Publication No. 2002-71331 (p. 3, 49th line in left column to p. 4, 21st line in right column, FIG. 1)}
Another inspection uses a reticle (optical mask or photomask) and its layout method of the following type. For example, each of a plurality of shots constituted of a plurality of different chips is disposed on a reticle in such a manner that all or some of chips having the same pattern are aligned along a row or column direction or directions to inspect the mask. (Refer to Patent Document 3: Japanese Unexamined Patent Publication No. HEI-10-73916 (p. 3, 41st line in left column to p. 4, 3rd line, FIG. 1))